RESUME

Objective:

Employment with a company that will provide challenging digital design projects, good benefits, and solid leadership.

• ASIC Design and Technical Writing for IPSEC Network Processor. Implemented Triple DES, MD5, SHA-1, HMAC and CBC protocols, SPI-4.2 Serial Interface, dedicated microsequencer, multiport buffering mechanism, thread dispatcher.
• ASIC Design & Technical Writing for a series of third-level cache controller/bridge chips, mostly implemented between two Intel processor busses. These included Pentium Pro, Merced, and Foster processor support.
• Aided implementation of external tag RAM interface using synchronous SRAMs, and cache data RAM interfaces using SDRAM SIMMs.
• Implemented simulation environments using Verilog to test these designs.
• Implemented various C programs Perl scripts, and HTML/CGI scripts in support of these projects.

• Designed second level cache controller ASIC for Intel P54C processor board, using Verilog HDL.
• Designed high-speed split-transaction system bus.
• Wrote design specifications for ASIC, processor board and system bus.
• Implemented simulation models and stimulus vectors.
• Received two Unisys Achievement Awards for Excellence.
• Filed patent applications relating to project - 2 patents granted, 4 patents pending.
• Wrote and published article in trade journal describing project.

• Performed various project design and administrative functions at Unisys Corporation, including board design, technical writing and diagnostic coding.
• Performed system administration and CAE library management for a cluster of Mentor Graphics workstations.

• Designed a variety of boards, including serial communications, tape controllers, SCSI controllers, ISA and Microchannel co-processor boards, Arcnet controllers and assorted network hubs.
• System administrator and librarian for a small cluster of Mentor Graphics workstations.
• Network manager for all R&D systems.

• Designed 8086-based modem security system based on Multibus backplane.
• Wrote technical briefs and proposals, as well as contributing to patent disclosure, company's project and business plans.

• Supervised final implementation and testing of Berkeley Floating Point Accelerator Project.
• Performed testing and debugging, documented design, wrote support and test software, coordinated overall project.

Skill Set:

• Have programming experience in C, Pascal, Basic, Fortran, Verilog HDL, ABEL, Perl, HTML, plus assorted assembly, machine, and microcodes.
• Have extensive experience using UNIX/Linux, Apollo Aegis, Mac-OS, MS-DOS, and MS-Windows.
• Design environments include Mentor Graphics schematic entry, Cadnetix schematic entry, Cadence Composer and Synopsys Logic Synthesis tools.
• Have extensive experience with text editing and processing tools, including vi, troff, BBEdit, MS-Word 6 plus Adobe tools FrameMaker, Acrobat, InDesign and GoLive. Limited experience with Photoshop.

Education:

BS in EECS, College of Engineering, UC Berkeley, December 1981

Affiliations:

Institute of Electrical and Electronics Engineers (IEEE)
Association for Computing Machinery (ACM)

Avocations:

Writing, science fiction, film, music, model railroading, gaming, football, fencing, pool and volleyball.